Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.
One of the problems due to the scaling down of CMOS transistors is that the power consumption keeps increasing. This is partly because leakage currents are increasing (e.g. due to short channel effects) and because it becomes difficult to decrease the supply voltage. The latter is mainly due to the fact that the subthreshold slope is limited to minimally about 60 mV/decade, such that switching the transistor from ON to OFF needs a certain voltage variation and therefore a minimum supply voltage.
Tunnel field-effect transistors (TFETs) are typically advertised as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), because of their absence of short-channel effects and because of their resulting low off-currents. Another advantage of TFETs is that the subthreshold slope can be less than 60 mV/dec, the physical limit of conventional MOSFETs, such that potentially lower supply voltages can be used. However, TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier.
In US 2005/0274992, a method of fabricating an improved TFET using nanowires is disclosed. The method comprises forming in a nanotube (i.e. a nanowire with axial opening) an n-doped region and a p-doped region that are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer is deposited on the channel region of the transistor. The proposed structure still has the disadvantage of introducing new materials (carbon nanotubes).
To increase the on-current of a silicon TFET, suggestions have been made in literature by Bhuwalka et al. (IEEE transactions on electron devices Vol. 52, No. 7, July 2005) to add a small (about 3 nm wide) section of highly-doped Si1-xGex at the tunnel barrier. The Si1-xGex has a smaller band gap than Si such that the tunnel barrier width decreases due to the presence of this section. However, these structures with the Si1-xGex section can still not compete with conventional MOSFETs because of their low on-currents.
As a conclusion, there is still a need for an improved method of fabricating a nanowire tunnel field effect transistor.